
3. Timing Diagrams (for SPI Mode 0 (0, 0))
Figure 3-1.
Synchronous Data Timing
CS
V IH
V IL
t CSS
V IH
t CSH
t CS
SCK
SI
V IL
V IH
V IL
t SU
VALID IN
t WH
t H
t WL
t V
t HO
t DIS
SO
V OH
HI-Z
HI-Z
V OL
Figure 3-2.
Figure 3-3.
WREN Timing
WRDI Timing
12
AT25F1024A
3346G–SFLSH–7/07